Non-volatile semiconductor memory circuits

ABSTRACT

A non-volatile semiconductor memory circuit having at least one variable threshold FATMOS transistor in the cross-coupled lateral branches and a plurality of input switching transistors controlling operation of the circuit. Capacitive imbalance between the nodes of the circuit is reduced by having each transistor which is connected between a node and an input switching transistor driven by the same control signal as a corresponding transistor connected between the other node and an input switching transistor. This reduces the occurrence of wrong-state switching in the circuit during reading.

This is a continuation of application Ser. No. 256,647, filed Apr. 23, 1981, now abandoned.

FIELD OF INVENTION

This invention relates to non-volatile semiconductor memory circuits.

BACKGROUND OF INVENTION

Semiconductor memories can be classified as volatile (where stored information is lost upon power removal) and non-volatile (where stored information is maintained after power removal, and which can be accurately retrieved after subsequent power-up). Several types of non-volatile semi-conductor memories are known, notably based on MNOS transistors, FAMOS transistors, or FATMOS transistors. A description of prior MNOS and FAMOS memory circuits is given in U.S. Pat. No. 4,132,904. The latter patent, together with U.K. Specification No. 2,000,407 describe and claim FATMOS non-volatile latch memory circuits.

The FATMOS is basically a control gate plus floating gate MOS transistor with a portion of the floating gate lying close to the semiconductor substrate. When the source and drain connections are connected to an appropriate potential (one positive relative to the other) and a suitable potential of a first magnitude applied to the control gate, the transistor conducts. Upon removal of the control gate potential, conduction ceases. If a potential of a second and higher magnitude is applied to the control gate with the drain at zero voltage, the transistor again conducts, but in addition electric charges tunnel between the floating gate and the transistor substrate through the portion of the floating gate closest to the substrate. This charge remains on the floating gate even when the control gate potential is removed and increases the switching threshold of the device. This charge on the floating gate enables the transistor to be employed in a non-volatile memory, as described in U.K. Specification No. 2,00,407. The switching threshold of the FATMOS is returned to its original level by applying between the control gate and drain a potential of approximately the second and higher potential, but of opposite polarity.

In a typical example of an N-channel enhancement-type FATMOS, the area of the floating gate closest to the substrate overlies the drain of the transistors, although this is not essential and the area closest to the substrate can be elsewhere on the transistor. In normal, non-volatile operation of a latch including such a FATMOS device, a voltage of typically +5 to +7 volts is applied to the control gate of the FATMOS. To write non-volatile information into the latch, a voltage of typically +8 to +15 volts is applied to the control gate of the FATMOS. If power is removed from the latch and then subsequently restored, it settles into a logic state dictated by its state during the earlier non-volatile write operation.

Although FATMOS transistors work well when employed in non-volatile memory cells (see U.K. Specification No. 2,000,407) certain configurations of FATMOS transistors can sometimes be unpredictable during reading after the FATMOS's have been placed in their non-volatile written mode (higher threshold state). This unpredictability manifests itself by the FATMOS transistor(s) switching to the wrong state (i.e. a FATMOS with a charge retained on its floating gate being held "off" instead of "on" and vice-versa).

Wrong state switching during reading is particularly noticeable when the shift in the switching threshold of a FATMOS is low, as can occur towards the end of the life of a FATMOS or as a result of normal production variations. The low threshold shift increases the relative effect of other sources of imbalance in the memory cell which may override the effect of the threshold shift and cause the cell to go into the wrong state on reading.

The present invention is concerned with reducing the imbalance in a memory cell due to effects other than those produced by putting the FATMOS devices into their non-volatile modes, so as to improve the reliability of the cell when the threshold shifts are low.

SUMMARY OF THE INVENTION

According to the present invention there is provided a non-volatile semiconductor memory circuit having a pair of cross-coupled branches connectable across a common supply voltage, each branch including a complementary driver or load, a driver connected in series with the complementary driver or load at an output node and a plurality of input switching devices operable by input signals, at least one of said complementary drivers or loads, or drivers including an insulated gate field effect transistor (IGFET) having a threshold voltage which may be varied by raising its gate potential above a predetermined level relative to the potential on one of its electrodes so as to store data in the circuit, wherein a first transistor connected between the output node and an input switching device in one branch is arranged to be in the same state as a corresponding second transistor connected between the output node and an input switching device in the other branch when data stored in the circuit is being read out.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred features of the invention will now be described with reference to the accompanying drawing given by way of example in which:

FIG. 1 is an electrical circuit diagram of the memory circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is shown a CMOS non-volatile, flip-flop having P-channel complementary drivers (or loads) Q₁, Q₂, and N-channel drivers constituted by FATMOS devices Q₃, Q₄, and their series transistors Q₅, Q₆. The control gates of the transistors Q₁ to Q₆ are cross-coupled to the nodes of each opposite branch of the cell, such nodes being indicated as X₁ and X₂. The signal levels at these nodes set the output signals from the cell M and M. Input data signals to the cell D, D and a clocking signal CK control input switching transistors Q₇ to Q₁₄ to enable data to be written into the cell and read out when required. If the clocking signal CK is at its high level, the P-channel transistors Q₈, Q₁₀ will be "off" and the N-channel transistors Q₁₁, Q₁₃ will be "on", so that when the data signal D is "high", the P-channel transistor Q₇ is "off" and the N-channel transistor Q₁₂ is "on", which causes the node X₁ to drop to its logic "0" state, and conversely the signal D causes the P-channel transistor Q₉ to turn "on" and the N-channel transistor Q₁₄ to turn "off" allowing the node X₂ to go to its logic "1" state. In this way data is put into the cell from the input switching transistors when the clocking signal CK is high and can be held in a non-volatile written state by raising the electrode voltages on the FATMOS devices Q₃ and Q₄ with CK at its "low" level, in the manner described in the above mentioned UK Patent Specification No. 2,000,407.

When the clocking signal CK is at its "low" level the P-channel transistors Q₈ and Q₁₀ are "on" and the N-channel transistor Q₁₁ and Q₁₃ are "off", so that even if the value of the data signals D, D changes the flip-flop transistors Q₁ to Q₂ remain in the same state.

With the cell in its non-volatile written state one of the FATMOS devices will have a different charge stored on its floating gate than the other FATMOS device.

When voltage is then applied across the voltage rails V_(DD), V_(SS) this difference in charge gives the FATMOS transistors Q₃, Q₄ different threshold voltages and hence causes one of them to turn on before the other, tipping the flip-flop into the correct state corresponding to the data originally written into the cell.

This data is read out from the cell with the clocking signal CK at its "low" level.

However, during power-up, as the voltage rails V_(DD), V_(SS) move apart, any stray capacitance between either of the nodes X₁ or X₂ and one of the power rails will effect the voltages at the nodes. If the capacitance between node X₁ and one of the power rails is different from the capacitance between node X₂ and the same power rail then this will produce a voltage difference between the nodes during power-up which may be sufficient to override the difference in threshold voltage between the FATMOS transistors and cause the wrong one to turn on first, thus driving the flip-flop into the wrong state.

One source of stray capacitance in the circuit is the internal capacitance of the interconnections at each junction between transistors. These capacitances connect to the supply rails and combine in the circuit of FIG. 1 to give the effective stray capacitors C₁ -C₈. The size of these stray capacitors depend on the physical parameters of the various transistors and careful control of the design and production of the memory cell can ensure that C₁, C₂, C₅ and C₇ are substantially equal to C₃, C₄, C₆ and C₈ respectively. Thus the stray capacitors connected directly to the nodes X₁, X₂ can be balanced so that the capacitance at each node is the same. However, the capacitors C₇, C₈, C₅ and C₆ connect to the nodes via transistors Q₁, Q₂, Q₁₁ and Q₁₃ and the state of those transistors will therefore effect the capacitance at each node. In FIG. 1, Q₁₁ and Q₁₃ are both driven by the clocking signal CK so that they are always in the same state. Thus the stray capacitances C₅ and C₆ across the transistors Q₁₂ and Q₁₄ which are respectively in series with Q₁₁ and Q₁₃ are either both connected to the respective nodes or both disconnected, and the balance of capacitance at the nodes is maintained. If the transistors Q₁₁ and Q₁₃ were driven by different signals, such as D and D (Q₁₂ and Q₁₄ being driven by CK) then an imbalance in the capacitance at the nodes would be introduced which could cause wrongstate switching of the memory cell.

Since Q₁₁ and Q₁₃ are driven by CK, they will be both "off" during the read operation, which further ensures that any slight differences between C₅ and C₆ due to production variations or other factors will not effect the balance between the nodes if the memory cell is switched on in its data reading state.

The stray capacitors C₇ and C₈ connect to the nodes X₁, X₂ through the complementary driver or load transistors of the flip-flop Q₁ and Q₂, and do not effect the operation of the memory cell during reading since the capacitors C₇ and C₈ are shorted out by CK turning Q₈ and Q₁₀ "on". It will, however, be noted that the transistors Q₇, Q₈ and Q₉ Q₁₀ are connected to the nodes X₁, X₂ through transistors Q₁ and Q₂ and that since during reading these transistors Q₁ and Q₂ are initially in the same state any stray capacitance at the gates of transistors Q₇ and Q₉ will not imbalance the cell. Thus a further source of imbalance is removed by this particular configuration of the transistors Q₁, Q₂ and Q₇ to Q₁₀.

The cell shown in FIG. 1 has a CMOS configuration with FATMOS N-channel drivers. The converse configuration with FATMOS P-channel drivers is also possible.

The present invention is of particular benefit when used in combination with the precharging of latch nodes which is the subject of the co-pending U.S. Patent Application No. 101,968, filed Dec. 10, 1979 in the name of Colin Edwards, now U.S. Pat. No. 4,333,166. This precharging mainly concerns the possible problems of imbalance in the stray capacitors C₁ -C₄ and when combined with the present invention produces a further improvement in the reliability of the memory circuit.

In the circuit of FIG. 1 the P-type transistors have their substrates connected to V_(DD) and the N-type transistors have their substrate connected to V_(SS), as is conventional practise in such circuits.

This balancing of the capacitive loading at the nodes is not necessarily restricted to D-type circuits but is of general application in the design of non-volatile memory elements, in particular RAM cells. 

I claim:
 1. A non-volatile semiconductor memory circuit having a pair of branches, each branch including:a complementary driver or load (Q₁, Q₂); an insulated gate field effect transistor (IGFET) driver (Q₃, Q₄) connected in series with the complementary driver or load, with an output node (X₁, X₂) of the circuit being at the junction of the IGFET driver with the complementary driver or load; means for connecting the complementary driver or load (Q₁, Q₂) and the IGET driver (Q₃, Q₄) of both branches between a supply voltage (V_(DD), V_(SS)); and a plurality of input switches semiconductor devices (Q₇ -Q₁₄) operable by input signals (D, D, CK) to the circuit; wherein(1) at least one of said complementary drivers or loads, or IGFET drivers, is an insulating gate field effect transistor (IGFET) having a threshold voltage which may be varied by raising its gate potential above a predetermined level relative to the potential on one of its electrodes so as to store data in the circuit; (2) the output node on one branch (X₁) is connected to a connection to the supply voltage (V_(SS)) through a series connection of first (Q₁₁) and second (Q₁₂) said input switching semiconductor devices, said first (Q₁₁) device being adjacent the output node (X₁); (3) the output node of the other branch (X₂) is connected to a connection to the supply voltage (V_(SS)) through a series connection of third (Q₁₃) and fourth (Q₁₄) said input switching semiconductor devices, said third device (Q₁₃) being adjacent the output node; (4) said first (Q₁₁) and third (Q₁₃) devices are arranged to be in the same state when data stored in the circuit is being read out; and(5) the output node of said one branch (X₁) being connected to a gate terminal of said IGFET driver (Q₄) and the output node of the other branch (X₂) being connected to a gate terminal of said IGFET driver (Q₃) in the one branch driver (Q₃).
 2. A circuit as claimed in claim 1 wherein said first (Q₁₁) and second (Q₁₂) devices are in parallel with the IGFET driver (Q₃) of said one branch and said third (Q₁₃) and fourth (Q₁₄) devices are in parallel with the IGFET driver (Q₄) of said other branch.
 3. A circuit as claimed in claim 2 wherein said first (Q₁₁) and third (Q₁₃) devices are operated by a clocking signal (CK) which controls the transfer of data into the memory circuit and said second (Q₁₂) and fourth (Q₁₄) devices are operated by data signals (D, D).
 4. A circuit as claimed in claim 2 or 3 wherein said one branch has fifth (Q₇) and sixth (Q₈) input switching semiconductor devices in parallel to one another and in series between the complementary driver or load (Q₁) of said one branch and a connection to the supply voltage (V_(DD)), and said other branch has seventh (Q₉) and eighth (Q₁₀) input switching semiconductor devices in parallel to one another and in series between the complementary driver or load (Q₂) of said other branch and a connection to the supply voltage (V_(DD)), said fifth (Q₇), sixth (Q₈), seventh (Q₉) and eighth (Q₁₀) devices being operable by the same input signals (D, CK) as used for said first (Q₁₁) to fourth (Q₁₄) devices.
 5. A circuit as claimed in claim 1 wherein said input switching semiconductor devices are MOS transisters.
 6. A circuit as claimed in claim 1 wherein one or both of said IGFET drivers are variable threshold IGFETs. 